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VIPER28
Off-line high voltage converters
Features

800 V avalanche rugged power section PWM operation with frequency jittering for low EMI Operating frequency: - 60 kHz for L type - 115 kHz for H type Standby power < 50 mW at 265 Vac Limiting current with adjustable set point Adjustable and accurate over-voltage protection On-board soft-start Safe auto-restart after a fault condition Hysteretic thermal shutdown Delayed overload protection
DIP-7
Description
The device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of over-current protection, over-voltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption helps to meet the standby energy saving regulations. Advance frequency jittering reduces EMI filter cost. The extra power timer allows the management of output peak power for a designed time window. The high voltage start-up circuit is embedded in the device. Figure 1. Typical topology
+
DC input high voltage wide range

Application

Auxiliary power supply for consumer and home equipment ATX auxiliary power supply Low / medium power AC-DC adapters SMPS for set-top boxes, DVD players and recorders, white goods
+
DC Output voltage
DRAIN DRAIN EPT
VIPER28
GND VDD CONT FB
Table 1.
Device summary
Order codes VIPER28LN DIP-7 VIPER28HN Tube Package Packaging
September 2008
Rev 1
1/29
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Contents
VIPER28
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 4.2 4.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 6 7
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current mode conversion with adjustable current limit set point . . . . . . . 19 Over-voltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Feed-back and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 21 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24 Extra power management function (EPT) . . . . . . . . . . . . . . . . . . . . . . . . 24 2nd level over-current protection and hiccup mode . . . . . . . . . . . . . . . . . 25
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VIPER28
Contents
8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
Block diagram
VIPER28
1
Figure 2.
Block diagram
Block diagram
VDD Vcc DRAIN
LEB Internal Supply bus & Ref erence Voltages OSCILLATOR OLP TURN-ON LOGIC OTP S Q R Q 2nd OCP + 2nd OCP LOGIC OTP OVP OLP S R HV_ON SUPPLY & UVLO UVLO HV_ON Istart-up
EPT Tovl
EPTl Tov BLOCK
THERMAL SHUTDOWN
OVP DETECTION LOGIC PWM BLOCK + -
+ OVP Disable
BURST-MODE REFERENCES
FB
2
Table 2.
Typical power
Typical power
230 VAC Part number Adapter(1) 18 W Open frame(2) 24 W Adapter(1) 10 W 85-265 VAC Open frame(2) 13 W
VIPER28
1. Typical continuous power in non ventilated enclosed adapter measured at 50 C ambient. 2. Maximum practical continuous power in an open frame design at 50 C ambient, with adequate heat sinking.
4/29
+
CONT
-
SOFT START
OCP BLOCK
OCP
BURST
LEB PWM
Rsense BURST-MODE LOGIC BURST
GND
VIPER28
Pin settings
3
3.1
Pin settings
Connection diagram
Figure 3. Connection diagram (top view)
GND VDD CONT FB
DRAIN DRAIN
EPT BR
3.2
Pin description
Table 3.
N. 1 2
Pin description
Name GND VDD Function This pin represents the device ground and the source of the power section. Supply voltage of the control section. This pin also provides the charging current of the external capacitor during start-up time. Control pin. The following functions can be selected: 1. current limit set point adjustment. The internal set default value of the cycleby-cycle current limit can be reduced by connecting to ground an external resistor. 2. output voltage monitoring. A voltage exceeding 3 V shuts the IC down reducing the device consumption. This function is strobed and digitally filtered for high noise immunity. Control input for duty cycle control. Internal current generator provides bias current for loop regulation. A voltage below 0.6 V activates the burst-mode operation. A level close to 3.3 V means that the device is approaching the cycle-by-cycle over-current set point. This pin allows the connection of an external capacitor for the extra power management. If the function is not used, the pin has to be connected to GND. High voltage drain pin. The built-in high voltage switched start-up bias current is drawn from this pin too.
3
CONT
4
FB
5 7,8
EPT DRAIN
5/29
Electrical data
VIPER28
4
4.1
Electrical data
Maximum ratings
Table 4.
Symbol VDRAIN EAV IAR IDRAIN VCONT VFB VEPT VDD IDD PTOT TJ TSTG
Absolute maximum ratings
Pin 7, 8 7, 8 7, 8 7, 8 3 4 5 2 2 Parameter Drain-to-source (ground) voltage Repetitive avalanche energy (limited by TJ = 150 C) Repetitive avalanche current (limited by TJ = 150 C) Pulse drain current Control input pin voltage (with ICONT = 1 mA) Feed-back voltage EPT input pin voltage Supply voltage (IDD = 25 mA) Input current Power dissipation at TA < 50 C Operating junction temperature range Storage temperature Value 800 5 1.5 3 Self limited -0.3 to 5.5 5 Self limited 25 1 -40 to 150 -55 to 150 Unit V mJ A A V V V V mA W C C
4.2
Thermal data
Table 5.
Symbol RthJP RthJA
Thermal data
Parameter Thermal resistance junction pin Thermal resistance junction ambient
2
Max value 25 75 (1)
Unit C/W C/W
1. When mounted on a standard single side FR4 board with 100 mm (0.155 sq in) of Cu (35 m thick)
6/29
VIPER28
Electrical data
4.3
Electrical characteristics
(TJ = -25 to 125 C, VDD = 14 V; unless otherwise specified) Table 6.
Symbol VBVDSS IOFF
Power section
Parameter Break-down voltage OFF state drain current Test condition IDRAIN = 1 mA, VFB = GND TJ = 25 C Min 800 60 7 14 40 Typ Max Unit V A pF
VDRAIN = max rating,
VFB = GND IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 25 C IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 125 C
RDS(on)
Drain-source on state resistance
COSS
Effective (energy related) output capacitance
VDRAIN = 0 to 640 V
Table 7.
Symbol Voltage
VDRAIN_START
Supply section
Parameter Test condition Min Typ Max Unit
Drain-source start voltage
60
80 -3
100 -4
V mA
IDDch
Start up charging current
VDRAIN = 120 V, VEPT = GND, VFB = GND, VDD = 4 V VDRAIN = 120 V, VEPT = GND, VFB = GND, VDD = 4 V after fault.
After turn-on IDD = 20 mA
-2
-0.4 8.5 23.5 13 7.5 4
-0.6
-0.8 23.5
mA V V
VDD VDDclamp VDDon VDDoff
VDD(RESTART)
Operating voltage range VDD clamp voltage VDD start up threshold VDD under voltage shutdown threshold VDD restart voltage threshold
VDRAIN = 120 V,
VEPT = GND, VFB = GND
14 8 4.5
15 8.5 5
V V V
VDRAIN = 120 V, VEPT = GND, VFB = GND
Current IDD0 IDD1 Operating supply current, not switching Operating supply current, switching VFB = GND, FSW = 0 kHz, VEPT = GND, VDD = 10 V 0.9 2.5 3.5 400 VDD = 7 V 270 mA mA mA uA uA
VDRAIN = 120 V, FSW = 60 kHz VDRAIN = 120 V, FSW = 115 kHz
IDD_FAULT IDD_OFF
Operating supply current, with protection tripping Operating supply current with VDD < VDD_OFF
7/29
Electrical data
VIPER28
Table 8.
Symbol
Controller section (TJ = -25 to 125 C, VDD = 14 V; unless otherwise specified)
Parameter Test condition Min Typ Max Unit
Feed-back pin VFBolp VFBlin VFBbm VFBbmhys IFB RFB(DYN) HFB CONT pin VCONT_l Low level clamp voltage ICONT = -100 uA 0.5 V Over-load shut down threshold Linear dynamics upper limit Burst mode threshold Burst mode hysteresis Feed-back sourced current Dynamic resistance VFB / ID Voltage falling Voltage rising VFB = 0.3 V 3.3 V < VFB < 4.8 V VFB < 3.3 V 14 2 -150 4.7 3.2 4.8 3.5 0.6 100 -200 -3 20 6 -280 5.2 3.7 V V V mV uA uA k V/A
Current limitation IDlim tSS TON_MIN td tLEB ID_BM Max drain current limitation Soft-start time Minimum turn ON time Propagation delay Leading edge blanking Peak drain current during burst mode VFB = 0.6 V 220 VFB = 4 V, ICONT = -10 A TJ = 25 C 0.75 0.80 8.5 400 100 300 160 480 0.85 A ms ns ns ns mA
Oscillator section
VIPER28L
FOSC
VIPER28H
Modulation depth Modulation frequency Maximum duty cycle
VDD = operating voltage range, VFB = 1 V
54 103
60 115 4 8 250
66 127
kHz kHz kHz kHz Hz
FD FM DMAX
VIPER28L VIPER28H
70
80
%
8/29
VIPER28
Electrical data
Table 8.
Symbol
Controller section (continued) (TJ = -25 to 125 C, VDD = 14 V; unless otherwise specified)
Parameter Test condition Min Typ Max Unit
Over-current protection (2nd OCP) IDMAX Second over-current threshold 1.2 A
Over-voltage protection VOVP TSTROBE Over-voltage protection threshold Over-voltage protection strobe time 2.7 3 2.2 3.3 V us
Extra power management IDLIM_EPT VEPT(STOP)
VEPT(RESTART)
Drain current limit with EPT function EPT shut down threshold EPT restart threshold Sourced EPT current
ICONT < -10 A TJ = 25 C ICONT < -10 A
85% IDLIM 4 0.6 5
A V V A
IEPT
Thermal shutdown TSD THYST Thermal shutdown temperature Thermal shutdown hysteresis 150 170 30 C C
9/29
Electrical data Figure 4. Minimum turn-on time test circuit
VIPER28
EPT
Figure 5.
OVP threshold test circuits
EPT
(The OVP protection is triggered after four consecutive oscillator cycles)
10/29
VIPER28
Typical electrical characteristics
5
Typical electrical characteristics
Figure 6. Current limit vs TJ Figure 7. Switching frequency vs TJ
Figure 8.
Drain start-up voltage vs TJ
Figure 9.
HFB vs TJ
Figure 10. Operating supply current (no switching) vs TJ
Figure 11. Operating supply current (switching) vs TJ
11/29
Typical electrical characteristics Figure 12. current limit vs RLIM
VIPER28 Figure 13. Power MOSFET on-resistance vs TJ
Figure 14. Power MOSFET break down voltage vs TJ
12/29
VIPER28 Figure 15. Thermal shutdown
Typical electrical characteristics
TJ
TSD THYST
VDD
VDD ON VDD OFF
t
VDD RESTART
VDS
t
t
13/29
Typical circuit
VIPER28
6
Typical circuit
Figure 16. Flyback application (basic)
EPT
Figure 17. Flyback application
EPT
14/29
VIPER28
Operation descriptions
7
Operation descriptions
VIPER28 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche rugged Power section. The controller includes: the oscillator with jittering feature, the start up circuits with soft-start feature, the PWM logic, the current limit circuit with adjustable set point, the second over-current circuit, the burst mode management circuit, the EPT circuit, the UVLO circuit, the auto-restart circuit and the thermal protection circuit. The current limit set-point is set by the CONT pin. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. All the fault protections are built in Auto Restart Mode with very low repetition rate to prevent IC's overheating.
7.1
Power section and gate driver
The Power section is implemented with an avalanche ruggedness N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The Power section has a BVDSS of 800 V min. and a typical RDS(on) of 7 at 25 C. The integrated SenseFET structure allows a virtually loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the Power section cannot be turned on accidentally.
7.2
High voltage startup generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When the HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the capacitor on the VDD pin. In case of Auto Restart mode after a fault event, the IDDch current is reduced to 0.6 mA, typ. in order to have a slow duty cycle during the restart phase. See Figure 18 on page 16.
15/29
Operation descriptions
VIPER28
7.3
Power-up and soft-start up
If the input voltage rises up till the device start level (VDRAIN_START), the VDD voltage begins to grow due to the IDDch current (see Table 6 on page 7) coming from the internal high voltage start up circuit. If the VDD voltage reaches VDDon threshold (~14 V) the power MOSFET starts switching and the HV current generator is turned OFF. See Figure 19 on page 17. The IC is powered by the energy stored in the capacitor on the VDD Pin, CVDD, until the selfsupply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than VDDoff threshold: a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. The following formula can be used for the VDD capacitor calculation: Equation 1
I DDch x t SSaux C VDD = ---------------------------------------V DDon - V DDoff
The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). During the converter start up time, the drain current limitation is progressively increased to the maximum value. In this way the stress on the secondary diode is considerably reduced. It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the feature is implemented for every attempt of start up converter or after a fault. See Figure 20 on page 17. Figure 18. Start up IDD current
IDD
VDS = 120V FSW = 0 kHz
2 mA
AFTER FAULT
1 mA IDD_FAULT IDD_OFF IDS_CH_FAULT -1 mA -2 mA -3 mA -4 mA
IDD0
VDDrestart
VDDoff
VDDon
VDD
IDS_CH
16/29
VIPER28
Operation descriptions Figure 19. Timing diagram: normal power-up and power-down sequences
Vin
VStart
VDD Vcc VDD ON Vcc VDD OFF Vcc VDD restart Vcc
regulation is lost here
t
VDRAIN
t
IDDch
3 mA
Icharge
t
Power -on
Normal operation
Power -off
t
Figure 20. Soft-start: timing diagram
I DRAIN tss
IDLIM
t
V FB V FB OLP
V FB_lin
t
17/29
Operation descriptions
VIPER28
7.4
Power down operation
At converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. The VDD voltage drops and when it falls below the VDDoff threshold (8 V typical) the power MOSFET is switched OFF, the energy transfer to the IC is interrupted and consequently the VDD voltage continues to decreases, Figure 19 on page 17. Later, if the VIN is lower than VDRAIN_START (80 V typical), the start up sequence is inhibited and the power down completed. This feature is useful to prevent converter's restart attempts and ensures monotonic output voltage decay during the system power down.
7.5
Auto restart operation
If after a converter power down, the VIN is higher than VDRAIN_START, the start up sequence is not inhibited and will be activated only when the VDD voltage drops down the VDDrestart threshold (4.5 V typical). This means that the HV start up current generator restarts the VDD capacitor charging only when the VDD voltage drops below VDDrestart. The scenario above described is for instance a power down because of a fault condition. After a fault condition, the charging current is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter phase. This feature together with the low VDDrestart threshold (4.5 V) ensures that, after a fault, the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput. The Figure 21 shows the IC behavioral after a short circuit event. Figure 21. Timing diagram: behavior after short circuit
VDD
VDD DDon VDD DDoff VDD(RESTART)
Short circuit occurs here
VDS
Trep < 0.03Trep
t
IDD_CH
0.6 mA
t t
FB Pin
4.8 V 3.3 V
t
t
7.6
Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching frequency is modulated by approximately 4 kHz (60 kHz version) or 8 kHz (115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes.
18/29
VIPER28
Operation descriptions
7.7
Current mode conversion with adjustable current limit set point
The device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. The VIPER28 has a default current limit value, IDLIM, that the designer can adjust according the electrical specification, by the RLIM resistor connected to the CONT see Figure 12 on page 12. The CONT pin has a minimum current sunk needed to activate the IDLIM adjustment: without RLIM or with high RLIM (i.e. 100 k) the current limit is fixed to the default value (see IDLIM, Table 8 on page 8).
7.8
Over-voltage protection (OVP)
The device can monitor the converter output voltage. This operation is done by CONT pin during power MOSFET OFF-time, when the voltage generated by the auxiliary winding tracks converter's output voltage, through turn ratio NAUX See Figure 22. -------------N SEC
In order to perform the output voltage monitor, the CONT pin has to be connected to the aux winding through a resistor divider made up by RLIM and ROVP (see Figure 17 (R3, R4 are respectively ROVP and RLIM)and Figure 23). If the voltage applied to the CONT pin exceeds the internal 3 V reference for four consecutive times the controller recognizes an over-voltage condition. This special feature uses an internal counter; that is to reduce sensitivity to noise and prevent the latch from being erroneously activated. see Figure 22 on page 20. The counter is reset every time the OVP signal is not triggered in one oscillator cycle. Referring to the Figure 17, the resistors divider ratio kOVP will be given by: Equation 2
V OVP k OVP = -------------------------------------------------------------------------------------------------N AUX -------------- ( V OUTOVP + V DSEC ) - V DAUX N SEC
Equation 3
R LIM k OVP = --------------------------------R LIM + R OVP
19/29
Operation descriptions Where:

VIPER28
VOVP is the OVP threshold (see Table 8 on page 8) VOUT OVP is the converter output voltage value to activate the OVP set by designer NAUX is the auxiliary winding turns NSEC is the secondary winding turns VDSEC is the secondary diode forward voltage VDAUX is the Auxiliary diode forward voltage ROVP together RLIM make the Output Voltage divider
Than, fixed RLIM, according to the desired IDLIM, the ROVP can be calculating by: Equation 4
1 - k OVP R OVP = R LIM x ---------------------k OVP
The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp. Figure 22. OVP timing diagram
VDS
t
VAUX
0
CONT (pin 4)
3V
t
t
STROBE
2 s
0.5 s
t
OVP
COUNTER RESET COUNTER STATUS FAULT
t
t
0 0 0 0 1 1 2 2 0 0 0 1 1 2 2 3 3 4
t t
NORMAL OPERATION
TEMPORARY DISTURBANCE
FEEDBACK LOOP FAILURE
20/29
VIPER28
Operation descriptions
7.9
About CONT pin
Referring to the Figure 23, through the CONT PIN, the below features can be implemented: 1. 2. Current Limit set point Over-voltage protection on the converter output voltage
The Table 9 on page 21 referring to the Figure 23, lists the external resistance combinations needed to activate one or plus of the CONT pin functions. Figure 23. CONT pin configuration
Auxiliary winding
Rlim
OVP DETECTION LOGIC From SenseFET
To OVP Protection
Table 9.
CONT pin configurations
Function / component IDlim reduction OVP IDlim reduction + OVP RLIM See Figure 6 80 K See Figure 6 ROVP No See Equation 4 See Equation 4 DAUX No Yes Yes
7.10
Feed-back and overload protection (OLP)
The VIPER28 is a current mode converter: the feedback pin controls the PWM operation, controls the burst mode and actives the overload protection of the device. Figure 24 on page 23 and Figure 25 show the internal current mode structure. With the feedback pin voltage between VFB_bm and VFBlin, (respectively 0.6 V and 3.5 V, typical values) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch off of the power MOSFET. The drain current is always limited to IDLIM value. In case of overload the feedback pin increases in reaction to this event and when it goes higher than VFBlin the drain current is limited or to the default IDLIM value or the one imposed through a resistor at the CONT pin (using the RLIM, see Figure 6 on page 11); the PWM comparator is disabled.
+
To PWM Logic
Daux
Rov p
CONT
SOFT START
OCP Current Limit Comparator
Curr. Lim. BLOCK
21/29
Operation descriptions
VIPER28
At the same time an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned off and the start up phase is activated with reduced value of Icharge to 0.6 mA. During the first start up phase of the converter, after the soft-start up time (typical value is 8.5 ms) the output voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches off the converter itself. To avoid this event, the appropriate feedback network has to be selected according to the output load. More the network feedback fixes the compensation loop stability. The Figure 24 on page 23 and Figure 25 on page 23 show the two different feedback networks. The time from the overload detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) can be calculated by CFB value (see Figure 24 on page 23 and Figure 25), using the formula: Equation 5
V FBolp - V FBlin T OLP - delay = C FB x --------------------------------------3A
In the Figure 24, the capacitor connected to FB pin (CFB) is used as part of the circuit to compensate the feedback loop but also as element to delay the OLP shut down owing to the time needed to charge the capacitor (see Equation 5). After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at VFBlin, the output capacitor could not be at its nominal value and the controller interpreters this situation as an overload condition. In this case, the OLP delay helps to avoid an incorrect device shut down during the start up face. Owing to the above considerations, the OLP delay time must be long enough to by-pass the initial output voltage transient and check the overload condition only when the output voltage is in steady state. The output transient time depends from the value of the output capacitor and from the load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay, an alternative compensation network can be used and it is showed in Figure 25 on page 23. Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole is usually used to compensate the high frequency zero due to the ESR (Equivalent Series Resistor) of the output capacitance of the fly-back converter. The mathematical expressions of these poles and zero frequency, considering the scheme in Figure 25 are reported by the equations below: Equation 6
fZFB =
1 2 CFB1 RFB1
22/29
VIPER28 Equation 7
Operation descriptions
fPFB =
RFB(DYN) + RFB1 2 CFB RFB(DYN) RFB1
(
)
Equation 8
fPFB1 =
1 2 CFB1 RFB1 + RFB(DYN)
(
)
The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Table 8 on page 8. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The equation Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike.
Figure 24. FB pin configuration
From sense FET PWM + PWM CONTROL Cfb BURST BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V To disable logic To PWM Logic
Figure 25. FB pin configuration
From sense FET PWM + PWM CONTROL Rfb1 Cfb BURST Cfb1 BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V To disable logic To PWM Logic
23/29
Operation descriptions
VIPER28
7.11
Burst-mode operation at no load or very light load
When the load decrease the feedback loop reacts lowering the feedback pin voltage. As the voltage reach the burst mode threshold VFBbm MOSFET stops switching. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding VFBbm threshold of 100 mV, the burst mode hysteresis typical value MOSFET the power device start switching again. Figure 26 shows this behavior called burst mode. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. During the burst mode operation the drain current is limited to ID_BM, 160 mA typ. value
Figure 26. Burst mode timing diagram, light load management
FB
100 mV 50 hyster.
VFBBM
I
DS
t
Normal -mode
Burst-mode
Normal -mode
t
7.12
Extra power management function (EPT)
Some applications need an extra power for a limited time window during which the converter regulation has to be guaranteed. The extra power management function allows to design a converter that can satisfy this request and is provided by the EPT pin, see Table 8 on page 9. This function requires the use of a capacitor on EPT pin (CEPT) that is charged or discharged by means of a 5 A current cycle by cycle. When the drain current raises over 85% of Idlim value, see IDLIM_EPT (Table 8 on page 8), the current generator charges CEPT while when the drain current is below IDLIM_EPT discharges the capacitor. If CEPT `s voltage reaches the VEPT threshold (typical, 4 V), the converter is shut down. After the converter shut down, the VDD voltage will drop below the VDD(ON) start up threshold (typ. 14.5 V) and according to the auto restart operation (see section 7.5) the VDD pin voltage have to fall below the VDD(RESTART) threshold (typical, 4.5V) in order to charge again the VDD capacitor. Moreover the PWM operation is enabled again only when the voltage on EPT pin, drop below the VEPT(RESTART) (typical, 0.6V). The low CEPT discharge current in combination with its low restart threshold, ensures safe operations and avoids
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VIPER28
Operation descriptions
overheating in case of repeated overload events. The value of CEPT has to be selected in order to prevent the device overheating. The EPT pin can be connected to GND if the function is not used.
7.13
2nd level over-current protection and hiccup mode
The VIPER28 is protected against short circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of fly-back transformer. Such as anomalous condition is invoked when the drain current exceed 1s A typical. To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a "warning state" is entered after the first signal trip. If in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the 2nd OCP threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF. The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor decays till the VDD under voltage threshold (VDDoff), which clears the latch. The start up HV current generator is still off, until VDD voltage goes below its restart voltage, VDD(RESTART). After this condition the VDD capacitor is charged again by 600 mA current, and the converter switching restart if the VDDon occurs. If the fault condition is not removed the device enters in auto-restart mode. This behavioral, results in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing diagram of Figure 27.
Figure 27. Hiccup-mode OCP: timing diagram
VDD Vcc
Secondary diode is shorted here
VDDON VDD OFF
VDD Vccrest
I DRAIN
I Dmax
t
VDS
t
t
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Package mechanical data
VIPER28
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 10. DIP-7 mechanical data
mm Dim. Typ A A1 A2 b b2 c D E E1 e eA eB L M
(6)(8)
Min
Max 5,33
0,38 3,30 0,46 1,52 0,25 9,27 7,87 6,35 2,54 7,62 10,92 3,30 2,508 0,50 0,40 0,60 0,60 0,548 2,92 3,81 2,92 0,36 1,14 0,20 9,02 7,62 6,10 4,95 0,56 1,78 0,36 10,16 8,26 7,11
N N1 O (7)(8)
1- The leads size is comprehensive of the thickness of the leads finishing material. 2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3- Package outline exclusive of metal burrs dimensions. 4- Datum plane "H" coincident with the bottom of lead, where lead exits body. 5- Ref. POA MOTHER doc. 0037880 6- Creepage distance > 800 V 7- Creepage distance 250 V 8- Creepage distance as shown in the 664-1 CEI / IEC standard.
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VIPER28 Figure 28. Package dimensions
Package mechanical data
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Revision history
VIPER28
9
Revision history
Table 11.
Date 30-Sep-2008
Document revision history
Revision 1 Initial release Changes
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VIPER28
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